The present invention relates to a manufacturing method of semiconductor devices. More specifically, the present invention relates to an improvement for introducing impurity ions into a semiconductor layer. Further, the present invention also relates to a method for manufacturing a semiconductor integrated circuit in which N-channel and P-channel thin-film transistors (hereinafter called xe2x80x9cTFTsxe2x80x9d) are formed on an insulating surface of a single substrate. The invention also relates to a manufacturing method of integrated circuits having TFTs such as a liquid crystal display device and a three-dimensional integrated circuit and in particular, integrated circuits (CMOS circuits) having complementary MOS (metal-oxide-semiconductor) or MIS (metal-insulator-semiconductor) field-effect devices.
In recent years, insulated-gate semiconductor devices in which a thin-film active layer (or active region) is formed on an insulating substrate have been investigated. In particular, thin-film insulated-gate transistors have been investigated eagerly. The TFTs are intended to be used for control of individual pixels in display devices having a matrix structure such as a liquid crystal display device, and classified into amorphous silicon TFTs, polycrystalline silicon TFTs, etc. in terms of a semiconductor material used and its crystal structure.
Polycrystalline TFTs are also used in a single crystal silicon integrated circuit (SOI technique), as load transistors in a highly integrated SRAM, for instance. Amorphous silicon TFTs are hardly used in this application.
A semiconductor circuit formed on an insulating substrate can operate at very high speed, because it is free of capacitive coupling between the substrate and the wiring. Techniques have been developed which are intended to use such a semiconductor circuit as an ultrahigh-speed microprocessor or memory.
Since amorphous semiconductors generally have a small electric field mobility, they cannot be used for a TFT that is required to operate at high speed. Further, amorphous silicon of P-type has a very small electric field mobility to disable manufacture of a P-channel TFT (PMOS TFT). Therefore, a complementary MOS (CMOS) circuit cannot be formed by combining PMOS TFTs with N-channel TFTs (NMOS TFTs) in the case of using amorphous silicon.
In contrast polycrystalline semiconductors have a larger electric field mobility than amorphous semiconductors and, therefore, can operate at high speed. For example, there has been reported a TFT which uses a silicon film re-crystallized by laser annealing and has an electric field mobility as large as 300 cm2/Vs. This is a very large value in view of the fact that a MOS transistor formed on an ordinary single crystal silicon substrate has an electric field mobility of about 500 cm2/Vs. In contrast to the fact that a MOS circuit formed on a single crystal silicon has a limited operating speed due to parasitic capacitances between the substrate and the wiring, a TFT circuit, which is formed on an insulating substrate, is free of such a limitation, to assure a very-high-speed operation.
Further, polycrystalline silicon can provide both NMOS TFTs and PMOS TFTs in a similar manner, to enable manufacture of a CMOS circuit. For example, in an active matrix type liquid crystal display device, a device having a monolithic structure is known in which not only an active matrix portion but also peripheral circuits (drivers etc.) are composed of CMOS polycrystalline TFTs.
These features of the TFT are considered also in the above-mentioned TFTs used in a SRAM, in which PMOS TFTs are used as load transistors.
The thickness of an active layer of a TFT should be 100-2,000 xc3x85 and, preferably, 200-1,000 xc3x85. For example, in a doping step of TFTs, doping impurities need to be implanted into a layer of the above thickness at an optimum concentration. Further, in general, a gate insulating film formed on the active layer of a TFT should be 500-3,000 xc3x85, which is thicker than that of a VLSI. Therefore, the direct application of a doping technique in the conventional semiconductor integrated circuit technologies, particularly through-doping, causes some difficulties. The through-doping is a technique in which an active layer (semiconductor surface) is doped with a gate insulating film formed thereon.
For example, in the case of implanting boron (mass number 11) as P-type impurities, through-doping with ions of boron and hydrogen bromide can be performed at a relatively low acceleration voltage of less than 70 kV, for instance 40-65 kV, because they are light. However, in the case of implanting phosphorus (mass number 31) or arsenic (75) as N-type impurities ions of phosphorus and hydrogen phosphide need to be accelerated at a high voltage of more than 80 kV, for instance 85-110 kV, because they are heavy. Where a substrate having an insulating surface is irradiated with ions having such a high energy, device characteristics are likely deteriorated by, for instance, charge-up of the substrate. In addition, where an organic material such as a resist is applied as a mask to a substrate to effect selective ion implantation, it may be carbonized to make its peeling difficult.
In view of the above circumstances in the art, an object of the present invention is to provide a most suitable doping technique. More specifically, although not exclusively, it is an object of the present invention to form a CMOS device with a high efficiency.
According to the invention, in the case of implanting a light element, for instance, boron, impurities are implanted into an active layer through a gate insulating film. On the other hand, in the case of implanting a heavy element such as phosphorus or arsenic into an active layer, doping is performed after at least a portion of the gate insulating film in a region for implantation is removed or made thinner to allow a sufficient amount of the heavy element to reach the active layer.
With the above technique, the acceleration voltage of ions including heavy ions of phosphorus, arsenic or the like can be reduced to as low a voltage as 10-30 kV. Since an amount of ions which are conventionally absorbed by a gate insulting film now effectively reach a source and a drain, the necessary dose can be reduced. Further, as a result of these advantages, the invention can solve the charge-up problem and the difficulty of peeling off a mask material.
FIGS. 1(A)-1(E) show manufacturing steps according to a first embodiment of the present invention;
FIGS. 2(A)-2(E) show manufacturing steps according to a second embodiment of the invention;
FIGS. 3(A)-3(F) show manufacturing steps according to a third embodiment of the invention;
FIGS. 4(A) and 4(B) show liquid crystal display devices to which the manufacturing steps of FIGS. 2(A)-2(E) are to be applied;
FIGS. 5(A)-5(E) show manufacturing steps according to a fourth embodiment of the invention; and
FIGS. 6(A)-6(D) show manufacturing steps according to a fifth embodiment of the invention.